Parameterised reconfiguration is a method for dynamic circuit specialization on FPGAs. The main advantage of this new concept\r\nis the high resource efficiency. Additionally, there is an automated tool flow, TMAP, that converts a hardware design into a more\r\nresource-efficient run-time reconfigurable design without a large design effort. We will start by explaining the core principles\r\nbehind the dynamic circuit specialization technique. Next, we show the possible gains in encryption applications using an AES\r\nencoder. Our AES design shows a 20.6% area gain compared to an unoptimized hardware implementation and a 5.3% gain\r\ncompared to a manually optimized third-party hardware implementation. We also used TMAP on a Triple-DES and an RC6\r\nimplementation, where we achieve a 27.8% and a 72.7% LUT-area gain. In addition, we discuss a run-time reconfigurable DNA\r\naligner.We focus on the optimizations to the dynamic specialization overhead. Our final design is up to 2.80-times more efficient\r\non cheaper FPGAs than the original DNA aligner when at least one DNA sequence is longer than 758 characters. Most sequences\r\nin DNA alignment are of the order 213.
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